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ASAHI KASEI
[AKD4682-A]
AKD4682-A
AK4682 Evaluation Board Rev.0
FEATURE AKD4682-A is an evaluation board for AK4682, a single chip 24bit CODEC that has two channels of ADC and four channels of DAC. This board has interfaces with AKM's evaluation boards for A/D converter and D/A converter and makes easy to evaluate AK4682. Also this board has the digital audio interface and then achieves the interface with digital audio systems via RCA connector. Ordering guide
AKD4682-A --- AK4682 Evaluation Board 10 wire flat cable for connection with printer port of PC (IBM-AT compatible machine), control software for AK4682, driver for control software on Windows 2000/XP are packed with this. Control software does not work on Windows NT Windows 2000/XP needs an installation of driver. Windows 95/98/ME does not need an installation of driver.
FUNCTION On-board clock generators (AK4114 x2) Compatible with 2 types of digital audio interface - RCA (S/PDIF) input/output - 10pin headers for interfacing with external data source (x2) RCA connectors for clock input with external clock source 10pin headers for register control
GND +9V Regulator Regulator +5V +3.3V EXA
LOUT1/ROUT1
AK4114 (DIR) PORT A 10pin Header
RCA IN
LOUT2/ROUT2
AK4682
LOUT3/ROUT3
Control Data 10pin Header PORT B 10pin Header AK4114 (DIT)
RCA OUT
LINA/RINA
EXB
(Note) Each AK4114 integrates DIR, DIT and X'tal oscillator. Figure 1. AKD4682-A Block Diagram (* Circuit diagram and PCB layout are attached at the end of this manual.)
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ASAHI KASEI
[AKD4682-A]
EVALUATION BOARD MANUAL
Operating sequence 1. Set up power supply lines.
Name of Jack AVDD1 Color of Jack Orange Voltage Used for AVDD1 and DVDD1 of AK4682 Comment and attention Default
+4.5+5.5V
AVDD2
Orange
+4.5+5.5V
AVDD2 and DVDD2 of AK4682
D3.3V
Orange
+3.0+3.6V
Power supply of logic
TVDD (4682) PVDD AVSS1 AVSS2 DGND
Orange
+2.7+5.5V
TVDD of AK4682 TVDD of AK4114 PVDD of AK4682 Regulator Analog Ground Analog Ground Digital Ground
Should be always connected when JP25 (AVDD1_SEL) is set to AVDD1 side. Can be open when JP25 (AVDD1_SEL) is set to REG side. Should be always connected when JP26 (AVDD2_SEL) is set to AVDD2 side. Can be open when JP26 (AVDD2_SEL) is set to AVDD1 side. Should be always connected when JP45 (D3.3V_SEL) is set to D3.3V side. Can be open when JP45 (D3.3V_SEL) is set to REG side. Should be always connected when JP32 (TVDD_SEL) is set to TVDD side. Can be open when JP32 (TVDD_SEL) is set to REG side. Should be always connected
Open
Open
Open
Open
Red Black Black Black
+9+12V 0V 0V 0V
+9V 0V 0V 0V
Should be always connected Should be always connected Should be always connected Table 1. Power supply lines
Each supply line should be distributed from the power supply unit. 2. Set up evaluation mode and jumper pins. (Refer to the following item.) 3. Connect cables. (Refer to the following item.) 4. Power on. The AK4682 should be reset once bringing PDN (SW1) "L" upon power-up. 5. Set up control software registers. (Refer to the following item.)
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ASAHI KASEI
[AKD4682-A]
Evaluation modes (1) DAC with external DIR 1. Connection of connector For digital (S/PDIF) input, RCA connector J22 (PORTA_RX0) is available. For analog output, RCA connector J15 (LOUT1) and JP28 (ROUT1) are available. 2. Setting of jumper pin Setting of interface signal of PORTA: AK4114 (U7) is as follows. (Default input of PORTA is SDTIA1.) Jumper Default JP10
XTIA
JP13
SDTIA1_SEL
JP14
SDTIA2_SEL
JP16
MCLKA_SEL
JP17
BICKA
JP18
LRCKA
Open
DIR
GND
MCKO1
Short
Short
Table 2. Setting of interface signal of PORTA: AK4114 (U7) (1/3) 3. Setting of toggle switch Switch Default SW3 H
Table 3. Setting of interface signal of PORTA: AK4114 (U7) (2/3) 4. Setting of DIP switch Switch Default SW2 DIF0 H DIF1 L DIF2 H CM0 L OCKS0 L OCKS1 L
Table 4. Setting of interface signal of PORTA: AK4114 (U7) (3/3) (2) ADC with external DIT 1. Connection of connector For analog input, RCA connector J3 (LINA)/J6 (RINA), J7 (LINB)/J9 (RINB) are available. Setting of jumpers without inputs are open. For digital (S/PDIF) output, RCA connector J26 (PORTB_TX1) is available. 2. Setting of jumper pin Setting of analog inputs. Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6 JP39 (LIN1)/ JP33 (RIN1) LINA/RINA Open Open Open Open Open JP40 (LIN2)/ JP34 (RIN2) Open LINA/RINA Open Open Open Open JP41 (LIN3)/ JP35 (RIN3) Open Open LINA/RINA Open Open Open JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINA/RINA Open Open JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINA/RINA Open JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINA/RINA (Default)
Table 5. Setting of inputs through LINA/RINA
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ASAHI KASEI
[AKD4682-A]
Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6
JP39 (LIN1)/ JP33 (RIN1) LINB/RINB Open Open Open Open Open
JP40 (LIN2)/ JP34 (RIN2) Open LINB/RINB Open Open Open Open
JP41 (LIN3)/ JP35 (RIN3) Open Open LINB/RINB Open Open Open
JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINB/RINB Open Open
JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINB/RINB Open
JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINB/RINB
Table 6. Setting of inputs through LINB/RINB Setting of interface signal of PORTB: AK4114 (U10) is as follows. X3 (12.288MHz) is used as Clock (256fs) . Jumper Default JP20
EXA50
JP27
MCLKB_SEL1
JP28
BICKB_SEL
JP29
LRCKB_SEL
JP46
MCLKB_SEL2
Open
Open
BICK
LRCK
MCKO1
Table 7. Setting of interface signal of PORTB: AK4114 (U10) (1/3) 3. Setting of toggle switch Switch Default SW5 H
Table 8. Setting of PORTB: AK4114 (U10) (2/3) 4. Setting of DIP switch Switch Default SW4 DIF0 H DIF1 L CM0 H OCKS0 L OCKS1 L MSB L
Table 9. Setting of interface signal of PORTB: AK4114 (U7) (3/3) (3) Analog input to analog output (Through: Analog input Analog output) 1. Connection of connector For analog input, RCA connector J3 (LINA)/J6 (RINA), J7 (LINB)/J9 (RINB) are available. Setting of jumpers without inputs are open. For analog output, RCA connector J15 (LOUT1)/J28 (ROUT1), J16 (LOUT2)/J18 (ROUT2), J17 (LOUT3)/J27 (ROUT3) are available. 2. Setting of jumper pin Setting of analog inputs. Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6 JP39 (LIN1)/ JP33 (RIN1) LINA/RINA Open Open Open Open Open JP40 (LIN2)/ JP34 (RIN2) Open LINA/RINA Open Open Open Open JP41 (LIN3)/ JP35 (RIN3) Open Open LINA/RINA Open Open Open JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINA/RINA Open Open JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINA/RINA Open JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINA/RINA (Default)
Table 10. Setting of inputs through LINA/RINA -42007/02
ASAHI KASEI
[AKD4682-A]
Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6
JP39 (LIN1)/ JP33 (RIN1) LINB/RINB Open Open Open Open Open
JP40 (LIN2)/ JP34 (RIN2) Open LINB/RINB Open Open Open Open
JP41 (LIN3)/ JP35 (RIN3) Open Open LINB/RINB Open Open Open
JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINB/RINB Open Open
JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINB/RINB Open
JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINB/RINB
Table 11. Setting of inputs through LINB/RINB 3. Setting of toggle switch Switch Default SW3 L SW5 H
Table 12. Setting of interface signal of PORTB: AK4114 (U7, U10) (4) Analog input to analog output with external DIR (Analog input ADC DAC Analog output) 1. Connection of connector For analog input, RCA connector J3 (LINA)/J6 (RINA), J7 (LINB)/J9 (RINB) are available. Setting of jumpers for unused inputs are open. For analog output, RCA connector J15 (LOUT1)/J28 (ROUT1), J16 (LOUT2)/J18 (ROUT2), J17 (LOUT3)/J27 (ROUT3) are available. * X2 is available for clock. X2 is the X'tal for 11.2896MHz on the evaluation board. Change the X'tal depends on Fs. 2. Setting of jumper pin Setting of analog inputs. Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6 JP39 (LIN1)/ JP33 (RIN1) LINA/RINA Open Open Open Open Open JP40 (LIN2)/ JP34 (RIN2) Open LINA/RINA Open Open Open Open JP41 (LIN3)/ JP35 (RIN3) Open Open LINA/RINA Open Open Open JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINA/RINA Open Open JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINA/RINA Open JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINA/RINA (Default)
Table 13. Setting of inputs through LINA/RINA Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6 JP39 (LIN1)/ JP33 (RIN1) LINB/RINB Open Open Open Open Open JP40 (LIN2)/ JP34 (RIN2) Open LINB/RINB Open Open Open Open JP41 (LIN3)/ JP35 (RIN3) Open Open LINB/RINB Open Open Open JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINB/RINB Open Open JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINB/RINB Open JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINB/RINB
Table 14. Setting of inputs through LINB/RINB
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ASAHI KASEI
[AKD4682-A]
Setting of interface signal of PORTA: AK4114 (U7) is as follows. (Default input of PORTA is SDTIA1.) JP10 JP13 JP14 JP16 Jumper
XTIA SDTIA1_SEL SDTIA2_SEL
JP17
BICKA
JP18
LRCKA
MCLKA_SEL
Default
Open
DIR
GND
MCKO1
Short
Short
Table 15. Setting of interface signal of PORTA: AK4114 (U7) (1/5) Setting of interface signal of PORTB: AK4114 (U10) is as follows. JP20 JP27 JP28 JP29 Jumper
EXA50 MCLKB_SEL1 BICKB_SEL
JP46
MCLKB_SEL2
LRCKB_SEL
Default
Open
Open
BICKA
LRCKA
MCLKA
Table 16. Setting of interface signal of PORTB: AK4114 (U10) (2/5) 3. Setting of toggle switch Switch Default SW3 H SW5 H
Table 17. Setting of interface signal of PORTB: AK4114 (U7, U10) (3/5) 4. Setting of DIP switch Switch Default SW2 DIF0 H DIF1 L DIF2 H CM0 H OCKS0 L OCKS1 L
Table 18. Setting of interface signal of PORTA: AK4114 (U7) (4/5) Switch Default SW4 DIF0 H DIF1 L CM0 H OCKS0 L OCKS1 L MSB L
Table 19. Setting of interface signal of PORTB: AK4114 (U7) (5/5)
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ASAHI KASEI
[AKD4682-A]
Register control
AKD4682-A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (uP-I/F) to PC by 10-line flat cable packed with this. Take care of the direction of connector. There is a mark at connector. Connect the mark of 10-pin connector to pin#6 of PORT2. (Figure 2.)
PORT2 1 UP-I/F 10
Connect PC
SCL SDA SDA (ACK)
RED 10-wire flat cable 10-pin connector
5 6 10-pin header
AKD4682-A
Figure 2. PORT2 pin layout Control software is packed with this evaluation board. Software operation procedure is included in evaluation board manual.
Set-up DIP switch (SW2)
No. 1 2 3 4 6 7 Name DIF0 DIF1 DIF2 CM0 Content Setting of AK4114 Audio Interface Format (Refer Table 20.) Default ON OFF ON OFF OFF OFF
Selection of AK4114 Clock Mode (Clock Source) (Refer Table 21.) OCKS0 Selection of AK4114 Master Clock Output frequency (Refer Table 22.) OCKS1 Table 20. Set up modes of AK4114 (U7) and AK4682 (U1) DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 DAUX SDTO
Mode 0 1 2 3 4 5 6 7
DIF2 0 0 0 0 1 1 1 1
24bit, Left justified 16bit, Right justified 24bit, Left justified 18bit, Right justified 24bit, Left justified 20bit, Right justified 24bit, Left justified 24bit, Right justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, I2S 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, I2S Table 21. AK4114 Audio Interface Format PLL X'tal Clock source SDTO ON ON(Note) PLL RX OFF ON X'tal DAUX Table 22. AK4114 Clock Mode (Clock Source)
LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I
BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs I/O O O O O O O I I

Mode 0 1
CM0 0 1

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ASAHI KASEI
[AKD4682-A]
No. 0 1 2 3
OCKS1 0 0 1 1
OCKS0 MCKO1 MCKO2 X'tal fs (max) 0 256fs 256fs 256fs 96 kHz 1 256fs 128fs 256fs 96 kHz 0 512fs 256fs 512fs 48 kHz 1 128fs 64fs 128fs 192 kHz Table 23. AK4114 Master Clock Output Frequency

Toggle switch
[SW1] PDN: Switch for power down reset of AK4682 (U1). Keep "H" during operation of AK4682 (U1). Power down reset of AK4682 will be done by setting SW1 to "L" once, after power on. [SW3] AK4114 (U7)-PDN: Switch for power down reset of AK4114 (U7). Keep "H" during operation of AK4114 (U7). Power down reset of AK4114 (U7) will be done by setting SW1 to "L" once, after power on. [SW5] AK4114 (U10)-PDN: Switch for power down reset of AK4114 (U10). Keep "H" during operation of AK4114 (U10). Power down reset of AK4114 (U10) will be done by setting SW1 to "L" once, after power on. LED indication [LED1] ERF: LED for output of AK4114 (U7): INT0. It turns on when output of AK4114 (U7): INT0 is "H". [LED2] ERF: LED for output of AK4114 (U10): INT0. It turns on when output of AK4114 (U10): INT0 is "H".
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ASAHI KASEI
[AKD4682-A]
Set up Jumper pins
Jumper JP39 (LIN1) JP40 (LIN2) JP41 (LIN3) JP42 (LIN4) JP43 (LIN5) JP44 (LIN6) JP33 (RIN1) JP34 (RIN2) JP35 (RIN3) JP36 (RIN4) JP37 (RIN5) JP38 (RIN6) JP10 (XTIA) JP13 (SDTIA1_SEL) JP14 (SDTIA2_SEL) JP16 (MCLKA_SEL) JP17 (BICKA) JP18 (LRCKA) JP27 (MCLKB_SEL1) JP28 (BICKB_SEL) JP29 (LRCKB_SEL) JP46 (MCLKB_SEL2) JP25 (AVDD1_SEL) JP26 (AVDD2_SEL) JP32 (TVDD_SEL) JP45 (D3.3V_SEL) JP19 (EXA50) JP20 (EXB50) Evaluation Mode 1 Open Open Open Open Open Open Open Open Open Open Open Open Open DIR GND MCKO1 Short Short Open Open Open Open 2 LINA Open Open Open Open Open RINA Open Open Open Open Open Open GND GND Open Open Open Open BICK LRCK MCKO1 3 LINA Open Open Open Open Open RINA Open Open Open Open Open Open GND GND Open Open Open Open Open Open Open 4 Open Open Open Open Open Open Open Open Open Open Open Open Open DIR GND MCKO1 Short Short MCLKA BICK LRCK MCKO1
REG REG REG REG
Open Open (Default)
REG REG REG REG
Open Open
REG REG REG REG
Open Open
REG REG REG REG
Open Open
Set up control software registers
After the reset, setting example files are available as follows in CD-ROM to set registers in each evaluation modes.
Evaluation Mode 1
ADC/DAC: ak4682_dac_mode1.akr
Evaluation Mode 2
ADC/DAC: ak4682_adc_mode2.akr
Evaluation Mode 3
ADC/DAC: ak4682_analog_through _mode3.akr
Evaluation Mode 4
ADC/DAC: ak4682_loopback_mode4.akr
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2007/02
ASAHI KASEI
[AKD4682-A]
Analog Input Circuit
C20 JP39 +
LINA LINB
LIN1
LIN1
2.2u
2 3 1
J3
LINA
MR-552LS
JP40
LINA LINB
LIN2
LIN2
AVSS1
JP41
LINA LINB
C109 + 2 3 1
LIN3
LIN3
J7
LINB
2.2u
JP42
LINA LINB AVSS1
MR-552LS
LIN4
LIN4
JP43
LINA LINB
LIN5
LIN5
JP44
LINA LINB
LIN6
LIN6
C25 JP33 +
RINA RINB
RIN1
RIN1
2.2u
2 3 1
J6
RINA
MR-552LS
JP34
RINA RINB
RIN2
RIN2
AVSS1
JP35
RINA RINB
C108 + 2 3 1
RIN3
RIN3
J9
RINB
2.2u
JP36
RINA RINB AVSS1
MR-552LS
RIN4
RIN4
JP37
RINA RINB RINA RINB
RIN5
RIN5
JP38
RIN6
RIN6
Figure 3. Analog Input Circuit For analog input, RCA connector: J3 (LINA), J6 (RINA), J7 (LINB), J9 (RINB) are available to use. Analog inputs are single-ended and input ranges of each channel are nominally 5.6 Vpp@5V.
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ASAHI KASEI
[AKD4682-A]
Analog Output Circuit
C35
22u
+
R55
C112 2 3 1 + J15
220
+ C37
LOUT1 ROUT1
22u
R64
R65
220
+ C113
LOUT1
R54
2 3 1
J28
ROUT1
10k PVSS
4.7n PVSS
MR-552LS
10k PVSS
4.7n PVSS
MR-552LS
C36
22u
+
R57
C41 2 3 1 + J16
220
+ C38
LOUT2 ROUT2
22u
R60
R61
220
+ C42
LOUT2
R56
10k PVSS
4.7n PVSS
MR-552LS
10k PVSS
2 3 1
J18
ROUT2
4.7n PVSS
MR-552LS
C39
22u
+
R59
C110 2 3 1 + J17
220
+ C40
LOUT3 ROUT3
22u
R62
R63
220
+ C111
LOUT3
R58
2 3 1
J27
ROUT3
10k PVSS
4.7n PVSS
MR-552LS
10k PVSS
4.7n PVSS
MR-552LS
Figure 4. Analog Output Circuit For analog output, RCA connector: J15 (LOUT1), J28 (ROUT1), J16 (LOUT2), J18 (ROUT2), J17(LOUT3), J27(ROUT3) are available to use. Analog outputs are single-ended and output ranges of each channel are nominally 5.6Vpp@5V. Output range: AOUT is proportional to AVDD2 (AOUT=2 x AVDD2/5 x 1.4 x 2 = 2 x 5/5 x 1.4 x 2 =5.6Vpp).
Digital Input Circuit (External DIR : PORTA)
J22
PORTA_RX0
2 3 1 R74
C46
MR-552LS
75
0.1u
DGND DGND Figure 5. Digital Input Circuit (External DIR)
For digital input, RCA connector: J22 (PORTA-RX0) is available.
Digital Output Circuit (External DIT : PORTB)
J26
PORTB_TX1
2 3 1 4
T3 DA02
R85 8 R84
MR-552LS
DGND1
1
240
5
150
DGND1 Figure 6. Digital Output Circuit (External DIT)
For digital output, RCA connector: J26 (PORTB-TX1) is available.
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ASAHI KASEI
[AKD4682-A]
Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4682-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4682-A by 10-line type flat cable (packed with AKD4682-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AKD4682-A Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive, and double-click the icon of "AKD4682-A.exe", and set up the control program. AKD4682-A.exe: AK4682-A control program 5. Then evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button.
Explanation of each buttons
1. [Port Reset]: 2. [Write default]: 3. [All Write]: 4. [Function1]: 5. [Function2]: 6. [Function3]: 7. [Function4]: 8. [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write]: Set up the USB interface board (AKDUSBIF-A). Initialize the registers. Write all registers data that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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ASAHI KASEI
[AKD4682-A]
Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". When writing the input data to register, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog]: Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal. Data Box: Input registers data in 2 figures of hexadecimal. When writing the input data to register, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog]: Dialog to evaluate ATT
This is a dialog corresponding to address: 08H, 09H, 0AH, 0BH, 0CH, and 0DH of AK4682. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to register by this interval. Step Box: Data changes by this step. Mode Select Box: With checking this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 Without checking this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 When writing the input data to register, click [OK] button. If not, click [Cancel] button.
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ASAHI KASEI
[AKD4682-A]
4. [Save] and [Open] 4-1. [Save]
Save the current register setting data to the file. The extension of file name is "akr". (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is "akr".
4-2. [Open]
The register setting data saved to the file by [Save] is written to register. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button.
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ASAHI KASEI
[AKD4682-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed. (1) Click [F3] Button. Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the [Function3] window. The extension of file name is "aks".
Figure 7. Window of [F3]
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ASAHI KASEI
[AKD4682-A]
6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 8 opens.
Figure 8. [F4] window
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ASAHI KASEI
[AKD4682-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 9.
Figure 9. [F4] window(2) (2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE]: The sequence file names can assign be saved. The file name is *.ak4. [OPEN]: The sequence file names assign that are saved in *.ak4 are loaded.
6-3. Note
(1) [Function4] doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
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ASAHI KASEI
[AKD4682-A]
7. [Function5 Dialog]
The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 10 opens.
Figure 10. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr). (2) Click [WRITE] button, then the register setting is executed.
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE]: The register setting file names assign can be saved. The file name is *.ak5. [OPEN]: The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change.
- 18 -
2007/02
ASAHI KASEI
[AKD4682-A]
Measure Result
1) ADC part [Measurement condition] * Measurement unit : Audio Precision * MCLK : 256fs (fs=48kHz) * BICK : 64fs * fs : 48kHz * BW : 20Hz20kHz (fs=48kHz) * Bit : 24bit * Power Supply : AVDD1=AVDD2=DVDD1=DVDD2=5V, TVDD=3V, PVDD =9V * Interface : External DIT (fs=48kHz,) * Temperature : Room Temp fs=48kHz (ADC) Parameter S/(N+D) DR DR S/N S/N Input signal 1kHz, -0.5dB 1kHz, -60dB 1kHz, -60dB No signal No signal Measurement filter 20kLPF 20kLPF 20kLPF, A-weighted 20kLPF 20kLPF, A-weighted Results Lch 90.7 93.5 96.1 93.5 96.1 [dB] Rch 90.9 93.6 96.1 93.6 96.1
- 19 -
2007/02
ASAHI KASEI
[AKD4682-A]
2) DAC part [Measurement condition] * Measurement unit : Audio Precision * MCLK : 256fs (fs=48kHz, 96kHz), 128fs (fs=192kHz) * BICK : 64fs * fs : 48kHz, 96kHz, 192kHz * BW : 20Hz20kHz (fs=48kHz), 20Hz40kHz (fs=96kHz), 20Hz40kHz (fs=192kHz) * Resolution : 24bit * Power Supply : AVDD1=AVDD2=DVDD1=DVDD2=5V, TVDD=3V, PVDD =9V * Interface : External DIR (48kHz, 96kHz, 192kHz) * Temperature : Room Temp fs=48kHz Parameter S/(N+D) DR DR S/N S/N fs=96kHz Parameter S/(N+D) DR DR S/N S/N fs=192kHz Parameter S/(N+D) DR DR S/N S/N Input signal 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB "0" data "0" data Measurement filter 40kLPF 40kLPF 22kLPF, A-weighted 40kLPF 22kLPF, A-weighted Results [dB] Lch 87.1 96.4 101.4 96.5 101.4 Rch 86.7 96.2 101.2 96.3 101.2 Input signal 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB "0" data "0" data Measurement filter 40kLPF 40kLPF 22kLPF, A-weighted 40kLPF 22kLPF, A-weighted Results [dB] Lch 87.2 96.6 101.4 96.6 101.4 Rch 86.8 96.3 101.2 96.3 101.2 Input signal 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB "0" data "0" data Measurement filter 20kLPF 20kLPF 22kLPF, A-weighted 20kLPF 22kLPF, A-weighted Results Lch 87.9 98.7 101.4 98.7 101.4 [dB] Rch 87.4 98.4 101.2 98.4 101.2
- 20 -
2007/02
ASAHI KASEI
[AKD4682-A]
1. ADC part (ADC fs=48kHz)
AK4682 FFT fs=48kHz -1.0dB input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 11. FFT(Input Frequency =1kHz,Input Level=-1.0dBFS)
AK4682 FFT fs=48kHz -60dB input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 12. FFT(Input Frequency =1kHz,Input Level=-60dBFS)
- 21 -
2007/02
ASAHI KASEI
[AKD4682-A]
(ADC fs=48kHz)
AK4682 FFT fs=48kHz No signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 13. FFT(noise floor)
AK4682 THD+N vs Input Level fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-45 -50 -55 -60 -65 -70 -75 d B F S -80 -85 -90 -95 -100 -105 -110 -115 -120 -120 -110 -100 -90 -80 -70 -60 dBr -50 -40 -30 -20 -10 +0
Figure 14. THD + N vs Input Level (Input Frequency =1kHz)
- 22 -
2007/02
ASAHI KASEI
[AKD4682-A]
(ADC fs=48kHz)
AK4682 THD+N vs Input Frequency fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-80 -82.5 -85 -87.5 -90 -92.5 -95 d B F S -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
Figure 15. THD + N vs Input Frequency (Input Level=-1.0dBFS)
AK4682 Linearity fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
-130
-120
-110
-100
-90
-80
-70 dBr
-60
-50
-40
-30
-20
-10
+0
Figure 16. Linearity (Input Frequency =1kHz)
- 23 -
2007/02
ASAHI KASEI
[AKD4682-A]
(ADC fs=48kHz)
AK4682 Frequency Respons fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 d B F S -0.9 -1 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 -2 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 17. Frequency Response (Input Level=-1.0dBFS)
AK4682 Crosstalk fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-70 -75 -80 -85 -90 -95 -100 -105 d B -110 -115 -120 -125 -130 -135 -140 -145 -150 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 18. Crosstalk (Input Level=-1.0dBFS)
- 24 -
2007/02
ASAHI KASEI
[AKD4682-A]
2. DAC part (DAC fs=48kHz)
AK4682 FFT fs=48kHz 0dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 19. FFT(Input Frequency =1kHz, Input Level=0dBFS)
AK4682 FFT(Out of Band Noise) fs=48kHz No signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k Hz 2k 5k 10k 20k 50k 100k
Figure 20. FFT(Input Frequency =1kHz, Input Level=0dBFS,Notch=on)
- 25 -
2007/02
ASAHI KASEI (DAC fs=48kHz)
AK4682 FFT fs=48kHz -60dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k
[AKD4682-A]
10k
20k
Figure 21. FFT(Input Frequency =1kHz, Input Level=-60dBFS)
AK4682 FFT fs=48kHz No signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 22. FFT(noise floor)
- 26 -
2007/02
ASAHI KASEI (DAC fs=48kHz)
AK4682 FFT(Out of Band Noise) fs=48kHz No signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k Hz 2k 5k 10k 20k
[AKD4682-A]
50k
100k
Figure 23. FFT(out-of-band noise)
AKM
AK4682 THD+N vs Input Level fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-80
-82.5 -85 -87.5 -90 -92.5 -95 d B r A -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -120 -110 -100 -90 -80 -70 -60 dBFS -50 -40 -30 -20 -10 +0
Figure 24. THD+N vs Input Level (Input Frequency =1kHz)
- 27 -
2007/02
ASAHI KASEI (DAC fs=48kHz)
AK4682 THD+N vs Input Frequency fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-70 -72.5 -75 -77.5 -80 -82.5 -85 d B r A -87.5 -90 -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 20 50 100 200 500 Hz 1k 2k 5k
[AKD4682-A]
10k
20k
Figure 25. THD+N vs Input Frequency (Input Level=0dBFS)
AKM
AK4682 Linearity fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+0 -10 -20 -30 -40 -50
d B r A
-60 -70 -80 -90 -100 -110 -120 -130 -140 -140
-130
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Figure 26. Linearity (Input Frequency =1kHz)
- 28 -
2007/02
ASAHI KASEI (DAC fs=48kHz)
AKM AK4682 Frequency Response fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+1 +0.8 +0.6 +0.4 +0.2 d B r A +0 -0.2 -0.4 -0.6 -0.8
[AKD4682-A]
-1 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 27. Frequency Response (Input Level=0dBFS)
AKM
AK4682 Crosstalk fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-90
-92.5 -95 -97.5 -100 -102.5 -105 -107.5 d B -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 28. Cross-talk (Input Level=0dBFS)
- 29 -
2007/02
ASAHI KASEI
[AKD4682-A]
(DAC fs=96kHz)
AK4682 FFT fs=96kHz 0dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Figure 29. FFT(Input Frequency =1kHz, Input Level=0dBFS)
AK4682 FFT(Notch) fs=96kHz 0dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Figure 30. FFT(Input Frequency =1kHz, Input Level=0dBFS,Notch=on)
- 30 -
2007/02
ASAHI KASEI
[AKD4682-A]
(DAC fs=96kHz)
AK4682 FFT fs=96kHz -60dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Figure 31. FFT(Input Frequency =1kHz, Input Level=-60dBFS)
AK4682 FFT fs=96kHz No signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Figure 32. FFT(noise floor)
- 31 -
2007/02
ASAHI KASEI
[AKD4682-A]
(DAC fs=96kHz)
AK4682 THD+N vs Input Level fs=96kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-80 -82.5 -85 -87.5 -90 -92.5 -95 d B r A -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -140 -130 -120 -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0
FigureFigure 33. THD+N vs Input Level (Input Frequency =1kHz)
AK4682 THD+N vs Input Frequency fs=96kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-70 -72.5 -75 -77.5 -80 -82.5 -85 d B r A -87.5 -90 -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Figure 34. THD+N vs fin (Input Level=0dBFS)
- 32 -
2007/02
ASAHI KASEI
[AKD4682-A]
(DAC fs=96kHz)
AK4682 Linearity fs=96kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
-130
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Figure 35. Linearity (Input Frequency =1kHz)
AK4682 Frequency Response fs=96kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+1 +0.8 +0.6 +0.4 +0.2 d B r A +0 -0.2 -0.4 -0.6 -0.8
-1 40
50
100
200
500
1k Hz
2k
5k
10k
20k
40k
Figure 36. Frequency Response (Input Level=0dBFS)
- 33 -
2007/02
ASAHI KASEI
[AKD4682-A]
(DAC fs=96kHz)
AK4682 Crosstalk fs=96kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-90 -92.5 -95 -97.5 -100 -102.5 -105 -107.5 d B -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Figure 37. Cross-talk (Input Level=0dBFS)
- 34 -
2007/02
ASAHI KASEI
[AKD4682-A]
(DAC fs=192kHz)
AK4682 FFT fs=192kHz 0dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 90 200 500 1k 2k Hz 5k 10k 20k 50k 80k
Figure 38. FFT(Input Frequency =1kHz, Input Level=0dBFS)
AK4682 FFT(Notch) fs=192kHz 0dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 90 200 500 1k 2k Hz 5k 10k 20k 50k 80k
Figure 39. FFT(Input Frequency =1kHz, Input Level=0dBFS,Notch=on,40kHzLPF)
- 35 -
2007/02
ASAHI KASEI
[AKD4682-A]
(DAC fs=192kHz)
AK4682 FFT fs=192kHz -60dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 90 200 500 1k 2k Hz 5k 10k 20k 50k 80k
Figure 40. FFT(Input Frequency =1kHz, Input Level=-60dBFS)
AK4682 FFT fs=192kHz No signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 90 200 500 1k 2k Hz 5k 10k 20k 50k 80k
Figure 41. FFT(noise floor)
- 36 -
2007/02
ASAHI KASEI
[AKD4682-A]
(DAC fs=192kHz)
AK4682 THD+N vs Input Level fs=192kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-80 -82.5 -85 -87.5 -90 -92.5 -95 d B r A -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -140 -130 -120 -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0
Figure 42. THD+N vs Input Level (Input Frequency =1kHz)
AK4682 THD+N vs Input Frequency fs=192kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-70 -72.5 -75 -77.5 -80 -82.5 -85 d B r A -87.5 -90 -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 90 200 500 1k Hz 2k 5k 10k 20k 40k
Figure 43. THD+N vs Input Frequency (Input Level=0dBFS)
- 37 -
2007/02
ASAHI KASEI
[AKD4682-A]
(DAC fs=192kHz)
AK4682 Linearity fs=192kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
-130
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Figure 44. Linearity (f Input Frequency =1kHz)
AK4682 Frequency Response fs=192kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
+1 +0.75 +0.5 +0.25 -0 -0.25 -0.5 d B r A -0.75 -1 -1.25 -1.5 -1.75 -2 -2.25 -2.5 -2.75 90 200 500 1k 2k Hz 5k 10k 20k 50k 80k
Figure 45. Frequency Response (Input Level=0dBFS)
- 38 -
2007/02
ASAHI KASEI
[AKD4682-A]
(DAC fs=192kHz)
AK4682 Crosstalk fs=192kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V,TVDD=3.3V,PVDD=9.0V
-80 -82.5 -85 -87.5 -90 -92.5 -95 -97.5 d B -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 90 200 500 1k 2k Hz 5k 10k 20k 50k 80k
Figure 46. Cross-talk (Input Level=0dBFS
- 39 -
2007/02
ASAHI KASEI
[AKD4682-A]
Revision History
Date Manual Board (YY/MM/DD) Revision Revision 07/02/19 KM086400 0 Reason First Edition Contents
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
- 40 -
2007/02
5
4
3
2
1
DVDD1
LIN6
LIN5
LIN4
RIN6
RIN5
RIN4
CN4 48pin_4
D D
48
47
46
45
44
43
42
41
40
39
38
RIN3
R12 (short)
R11 (short)
R10 (short)
R9 (short)
R8 (short)
R7 (short)
R6 (short)
37
R5 (short)
LIN3
AVSS1
46
43
40
47
44
41
48
45
42
39
38
37
U1 CN1 + C16 C17
48pin_3
NC
NC
DVDD1
LIN6
LIN5
LIN4
NC
RIN6
RIN5
RIN4
10u
1
DVSS1 MCLKB R13 (short) 4682_TVDD
C
0.1u
1 DVSS1
RIN3
LIN3
RIN2
36
R4 (short)
36
RIN2
DVSS1
2
2
MCLKB
LIN2
35
R3 (short)
35
LIN2
10u
C98
0.1u
C99
3
LRCKB
R14 (short)
4
BICKB
R15 (short)
5
SDTOB
R16 (short) PDN
6
7
LRCKA
R18 (short)
8
8
LRCKA
VCOM3
29
C94 C95
BICKA
R19 (short)
9
9
BICKA
VCOM36
28
MCLKA
R20 (short)
10
10
MCLKA
AVSS2
27
C87 C91
SDTIA1
R21 (short)
11
11
SDTIA1
AVDD2
26
SDTIA2
R22 (short)
12
12
SDTIA2 ROUT1 ROUT2 DVDD2 DVSS2 LOUT1 LOUT2 LOUT3 PVDD PVSS MSB SDA SCL
ROUT3
25
48pin_1
13
14
15
16
17
18
19
20
21
22
23
B
24
C12
C13
0.1u
+ C14
0.1u
+ C15
10u
10u
DVSS2
PVSS
13
14
15
16
17
18
19
20
21
22
23
CN2 48pin_2
R23 (short)
R24 (short) DVDD2
DVSS2
R25 (short) PVDD1
PVSS
A
24
LOUT1
MSB
LOUT2
ROUT1
ROUT2
LOUT3
SDA
SCL
5
4
3
+
0.1u
+
0.1u
+
+
3
TVDD
NC
34
34
C
4
LRCKB
RIN1
33
R2 (short)
33
RIN1
5
BICKB
LIN1
32
R1 (short)
32
LIN1
6
SDTOB
7
PDN
AK4682
AVDD1
31
31
AVDD1
0.1u
C97
+10u C96
AVSS1
30
C92 C93 AVSS1
30
AVSS1
0.1u
10u
29
10u
AVSS1
28
27
AVSS2 AVSS2
10u
26
AVDD2
25
ROUT3
CN3
B
A
Title Size A2 Date:
2
Document Number
AKD4682-A
AK4682
Sheet 1 of 1
1
Rev 0
Monday, November 20, 2006
5
4
3
2
1
D
D
C20 JP39
LINA LINB
+
J3
LINA
LIN1
LIN1
2.2u
2 3 1
MR-552LS
JP40
LINA LINB
LIN2
LIN2
AVSS1
JP41
LINA LINB
C109 +
LIN3
J7
LIN3
LINB
2.2u
JP42
2 3 1
MR-552LS
LINA LINB AVSS1
LIN4
LIN4
C
JP43
LINA LINB
C
LIN5
LIN5
JP44
LINA LINB
LIN6
LIN6
C25 JP33
RINA RINB
+
J6
RINA
RIN1
RIN1
2.2u
2 3 1
MR-552LS
JP34
RINA RINB
RIN2
RIN2
AVSS1
B
JP35
RINA RINB
C108 +
RIN3
J9
RIN3
RINB
B
2.2u
JP36
2 3 1
MR-552LS
RINA RINB AVSS1
RIN4
RIN4
JP37
RINA RINB
RIN5
RIN5
JP38
RINA RINB
RIN6
RIN6
A
A
Title Size A3 Date:
5 4 3 2
Document Number
AKD4682-A
LIN/RIN
1
Rev 0 1 of 1
Monday, September 11, 2006
Sheet
5
4
3
2
1
D
D
D3.3V
14
R35 R38 D3.3V
10k
470
3 7
U3B 4 74LS07
R39
100
SCL
D3.3V
14 1 7
U3A 2 74LS07
C
R40
C
10k
R36
470
R41
100
SDA
PORT2
A1-10PA-2.54DSA
1 2 3 4 5 10 9 8 7 6
SCL SDA SDA(ACK)
R44
(short)
R66 R48 D3.3V
10k 10k
DGND
uP-I/F
D3.3V
K
14
B
A
1
U4A 2 74HC14
14
D1 1S1588
R49
10k
D3.3V
3
D3.3V
U4B 4 74HC14
R51 PDN 100
B
H
SW1
L
C33
7
ATE1D-2M3 PDN DGND
0.1u
A
7
A
Title Size A3 Date:
5 4 3 2
Document Number
AKD4682-A
INPUT/OUTPUT
Sheet
1
Rev 0 of 1
Monday, November 20, 2006
1
5
4
3
2
1
D
D
C35
22u
+
R55
C112
LOUT1
R54 + C37
2 3 1
MR-552LS
+
220
J15
LOUT1 ROUT1
22u
R64
R65
220
+ C113
J28
ROUT1
2 3 1
MR-552LS
10k PVSS
4.7n PVSS
10k PVSS
4.7n PVSS
C
C
C36
22u
+
R57
C41
LOUT2
R56 + C38
2 3 1
MR-552LS
+
220
J16
LOUT2 ROUT2
22u
R60
R61
220
+ C42
J18
ROUT2
2 3 1
MR-552LS
10k PVSS
4.7n PVSS
10k PVSS
4.7n PVSS
C39
22u
+
R59
C110
LOUT3
R58 + C40
2 3 1
MR-552LS
+
220
J17
LOUT3 ROUT3
22u
R62
R63
220
+ C111
J27
ROUT3
2 3 1
MR-552LS
B
10k
B
4.7n PVSS
10k PVSS
4.7n PVSS
PVSS
A
A
Title Size A3 Date:
5 4 3 2
Document Number
AKD4682-A
LOUT/ROUT
1
Rev 0 1 of 1
Monday, September 11, 2006
Sheet
5
4
3
2
1
DGND
J22
PORTA_RX0
2 3 1
R74
C46
C45 10u
D3.3V
2
C47 0.1u
1
D3.3V
+ +
MR-552LS
D
75 DGND
R75
K A
D2 HSU119
D
0.1u
14
DGND
D3.3V
C48 0.47u
R76 18k
U14B 4 74HC14
3 7
U14A 2 74HC14
7
DGND
D3.3V
D3.3V
1 14
10k
H
C49 SW3
PORT A_DIR/4682
48 46 45 44 42 41 47 43 40
DIF0 DIF1 DIF2 CM0 OCKS0 OCKS1
SW2
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
U7
39
38
37
D3.3V D3.3V
7 INT0 36 1 14
U8A 2 74HC04 PORTA_OCKS0 R77 1k LED1
D3.3V
0.1u
ATE1D-2M3 DIR PORTA
AVSS
TEST1
VCOM
AVDD
INT1
RX3
RX2
RX1
RX0
NC
NC
R
ERF
K A
D3.3V
1
IPS0
DGND
2
RP1
NC
OCKS0
35
D3.3V
9 8 7 6 5 4 3 2 1 3 DIF0 OCKS1 34
PORTA_OCKS1
PORTA_CM0 PORTA_OCKS0 PORTA_OCKS1
4
TEST2
CM1
33
C
DGND
5 DIF1 CM0 32
PORTA_CM0
C
47k
DGND
6
NC
1
7
DIF2
AK4114
PDN
31
C50 5p
JP10 XTIA
EXA
XTI
30
X2 11.2896MHz
C51 5p
IPS1
XTO
DGND
9 P/SN DAUX 28
2
8
29
DGND
SDTOB MCLKA
10
XTL0
MCKO2
27
BICKA LRCKA
11
XTL1
BICK
26
B
12
VIN MCKO1 COUT UOUT DVDD BOUT VOUT TVDD DVSS DVSS LRCK TX0 TX1
SDTO
25
B
JP13 SDTIA1_SEL
DIR GND DIR GND
JP14 SDTIA2_SEL
SDTIA1
13
14
15
16
17
18
19
20
21
22
23
DGND
C52 0.1u
C53 0.1u
24
SDTIA2
+
1
2
1
+
C55 10u
2
JP16 MCLKA_SEL
C54 10u 4114_TVDD
DGND
D3.3V
MCKO2 MCKO1 DGND JP17 BICKA JP18 LRCKA
DGND
MCLKA BICKA LRCKA SDTOB
1 2 3 4 5
10 GND 9 8 SDTIA1 7 SDTIA2 6
14
EXA J29
A
D3.3V
1
U9A 2 74VHC04 EXA
PORT A
PORT4
A1-10PA-2.54DSA
DGND
A
2 3 4 5
1
BNC
JP19 EXA50
R87 50
DGND
Title Size A3 Date:
5 4 3 2
7
Document Number
AKD4682-A
PORT A
1
DGND
Rev 0 of 1
Monday, November 20, 2006
Sheet
1
5
4
3
2
1
DGND1
C57 10u D3.3V
J25
PORTB_RX0
2 3 1
R80
C56
2
C58 0.1u
1
D3.3V
+ +
MR-552LS
75 DGND1
R81
K A
D3 HSU119
D
0.1u
14
D
DVDD2 D3.3V
DGND1
C59 0.47u
R82 18k
6 7
U14C 5 74HC14
14
DGND1
D3.3V
D3.3V
8 7
U14D 9 74HC14
10k
L
C60
H
SW5
PORT B_DIT
48 46 45 44 42 41 47 43 40
AVSS
TEST1
VCOM
AVDD
INT1
RX3
RX2
RX1
RX0
NC
NC
DIF0 DIF1 CM0 OCKS0 OCKS1 MSB
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
U10
39
38
37
SW4
0.1u D3.3V
7 3 INT0 36 14
U8B 4 74HC04 PORTB_OCKS0
ATE1D-2M3 DIT PORTB
R
R83 1k
LED2
ERF
K A
D3.3V
1
IPS0
DGND
2
RP2
NC
OCKS0
35
C
9 8 7 6 5 4 3 2 1
47k
3
PORTB_CM0 PORTB_OCKS0 PORTB_OCKS1 MSB
DIF0
OCKS1
34
PORTB_OCKS1
4
TEST2
CM1
33
DGND1
5 DIF1 CM0 32
PORTB_CM0
C
DGND1
6 NC
7
DIF2
AK4114
PDN
31
C61 5p
JP27 MCLKA EXB MCLKB_SEL1
XTI
30
1
X3 12.288MHz
C62 5p
8
IPS1
XTO
29
DGND1
9 P/SN DAUX 28
2
DGND1
SDTOB
10
XTL0
MCKO2
27
MCLKB
11
XTL1
BICK
26
BICKB LRCKB
B
12
VIN MCKO1 COUT UOUT DVDD BOUT VOUT TVDD DVSS DVSS LRCK TX0 TX1
SDTO
25
B
13
14
15
16
17
18
19
20
21
22
23
C63 0.1u
C64 0.1u
+
1
2
1
+
2
PORT5 JP46
C65 10u 4114_TVDD J26
C66 10u
24
DGND1
DGND1
D3.3V R85
MCKO2 MCKO1 DGND1
MCLKA MCLKB_SEL2
A1-10PA-2.54DSA
MCLK BICKB LRCKB SDTOB
DGND1
PORTB_TX1
2 3 1 4
T3 DA02
8
R84
MR-552LS
DGND1
1 5
240 EXB J30
2 3 4 5 1
BNC
JP28
1 2 3 4 5
10 GND 9 8 7 6
14
150
D3.3V
U9B
PORT B
BICKA EXB BICKB_SEL JP29
A
3
4 7
74VHC04
A
DGND1
JP20 EXA50
R86 50
DGND1
LRCKA LRCKB_SEL Title Size A3 Date:
Document Number
AKD4682-A
PORT B
1
DGND1
5 4 3 2
Rev 0 of 1
Monday, November 20, 2006
Sheet
1
5
4
3
2
1
TM_AVDD1
L2
TM_PVDD
JP25
+
(short)
C67
AVDD1 REG
AVDD1_SEL + C68 C69
T4 NJM78M05FA L4
GND
R98 (short) AVDD1
47u AVSS1
3
OUT
IN
1
C70 +
PVDD1 (short)
C71
PVDD T-45(R)
AVDD1 T-45(O)
AVDD2 T-45(O)
TVDD T-45(O)
D3.3V T-45(O)
1
1
1
1
D
DVSS1
47u
2
1
0.1u AVSS2 AVSS2
0.1u AVSS2
47u AVSS2 TM_PVDD TM_AVDD2 TM_D3.3V TM_AVDD1 TM_TVDD
DGND T-45(B) AVSS1 T-45(B) AVSS2 T-45(B)
D
R94 DVDD1 (short) TM_AVDD2
L3
AVSS2
1
1
+
(short)
C74
JP26
R95 (short) AVDD2
47u AVSS2
AVDD2 R91 REG
AVDD2_SEL
DGND AVSS1
AVSS2
(short) R97
DVSS2
R90 DVDD2
C
T5 TA48M033F
(open)
C
IN
C79
GND
(short) TM_TVDD
L8
OUT
C80 + C81
DGND 0.1u 47u
1
DVSS2
0.1u
R96 (open)
+
(short)
C82
JP32
TVDD REG
TVDD_SEL
DVSS1 DGND1 DVSS1
47u DVSS1 4682_TVDD R93 4114_TVDD (short) TM_D3.3V
L9
B
PVSS
AVSS2
B
+
(short)
C114
JP45
47u DGND D3.3V
D3.3V D3.3V
D3.3V R92 REG
D3.3V_SEL
(short)
D3.3V
D3.3V
14
14
14
5
U3C 6 74LS07
5 7
U8C 6 74HC04 U8D 8 74HC04 U8E 10 74HC04 U8F 12 74HC04
5 7
U9C 6 74VHC04 U9D 8 74VHC04 U9E 10 74VHC04 U9F 12 74VHC04
14 13 7
U4F 12 74HC14 U4E 10 74HC14 C88 U4D 8 74HC14 U4C 6 74HC14 C89 C90 C100 C101
7
14
14
14
9 7
U3D 8 74LS07
14
for 74HC14(U4), 74LS07(U3)
D3.3V D3.3V
9 7
9 7
11 7
74HC04(U8), 74VHC04(U9), 74HC14(U14)
14
14
14
14
A
11 7
U3E 10 74LS07
14
11 7
11 7
9 7
13 7
U14F 12 74HC14 U14E 10 74HC14
0.1u
0.1u
0.1u
0.1u
0.1u
A
DGND
14
14
14
14
13 7
U3F 12 74LS07
13 7
13 7
5 7
11 7
14
Title Size A3 Date:
DGND
DGND
DGND
DGND
DGND
Document Number
AKD4682-A
Power Supply
Sheet
1
Rev 0 1 of 1
Monday, November 20, 2006
5
4
3
2

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